1. Field of the Invention
Example embodiments of the present invention relate to semiconductor memory devices, for example, apparatuses for setting and/or selecting a mode register set in response to an input address and methods for the same.
2. Description of the Conventional Art
Synchronous memory devices (e.g., DDR SDRAMs, etc.) may include a conventional mode register for setting various parameters corresponding to product specifications and/or a test mode register for improving product efficiency when analyzing memory devices. In this way, mode register setting operations may be carried out in response to a clock signal.
FIG. 1 is a block diagram of a conventional mode register setting apparatus for performing a test mode register setting operation. The test mode setting operation may be performed in response to a clock signal.
A mode register set (MRS) command may be applied to a synchronous semiconductor memory device together with an address set. The MRS may be used for determining various factors related to an operating mode of a synchronous semiconductor memory device, for example, CAS latency and/or burst length. When an MRS command is applied to the synchronous semiconductor memory device together with an address set (e.g., A7=‘1’), the synchronous semiconductor memory device may enter a test mode.
A test mode may be an operating mode for efficiently testing a semiconductor memory device when it is manufactured. A user may set parameters related to the operating mode of the semiconductor memory device, for example, CAS latency and/or burst length. The test mode may be set in response to an address applied with an MRS command during manufacture of the semiconductor memory device.
Referring to FIG. 1, the conventional mode register setting apparatus may include a command decoder 11, an address set decoder 12, and/or a D flip-flop 13.
The command decoder 11 may output an MRS command MRS CMD in response to a plurality of input signals. The plurality of input signals may include a chip selection signal /CS, a row address strobe signal /RAS, a column address signal /CAS, and/or a write enable signal /WE. The command decoder 11 may output an MRS command MRS CMD with a logic high level in synchronization with a clock signal CLK when the chip selection signal /CS, the row address strobe signal /RAS, the column address signal /CAS, and/or the write enable signal /WE become logic low level.
The address set decoder 12 may output an address set signal MRS CODE in response to a plurality of memory address signals A0 through An-1. The address set signal MRS CODE may be enabled when the plurality of memory address signals A0 through An-1 match a given, desired, or designated address set.
The D flip-flop 13 may receive the MRS command MRS CMD output by the command decoder 11 through a clock input port and may receive the address set signal MRS CODE through a D input port. The D flip-flop 13 may be set in response to the address set signal MRS CODE and the MRS command MRS CMD, and may output a test mode activation signal TM. The test mode activation signal TM may enable a test mode.
The conventional mode register setting apparatus of FIG. 2 operates in synchronization with the clock signal CLK which may restrict the frequency of a test MRS as the frequency of the semiconductor memory device increases.
FIG. 2 is an example timing diagram illustrating a tCK Schmoo analysis during a clock period T1. The clock period T1 may correspond to a mode register setting period and/or a normal mode operating period. A test MRS command may be applied during a mode register setting period. In one example, if a tCK limit is detected before test MRS command application, a desired test mode may not be set as desired. This may limit the analysis of tCK margin variations in a normal mode. Accordingly, the tCK Schmoo analysis may not be performed as desired.
FIG. 3 is an example timing diagram illustrating a tCK Schmoo analysis during a clock period T2. The clock period T2 may correspond to a mode register setting period. A clock period T1 may correspond to a normal mode operating period. The detection of a tCK limit at the beginning of a mode register setting period may be suppressed due to the clock period being T2. Thus, the tCK Schmoo analysis may be carried out in a normal mode operating period. However, the example shown in FIG. 2 may result in varying clock periods and/or frequency variations (e.g. DLL locking).